1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FinFET includes a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc. In some approaches, fins of the FinFET are created by a process that is similar to self-aligned double patterning. The process involves patterning of a spacer and deposition of liners on top of one or more hardmasks. The spacer is then etched away, followed by the hardmask, leaving behind fins. However, it currently is not possible to obtain a FIN-free region due to the nature of the hardmask etch process.
Optical metrology is commonly employed in process control applications in the semiconductor manufacturing industry due to optical metrology's non-contact and non-destructive nature. FinFETs raise new metrology complexities, as the entire 3D structure becomes critical for process control, including fin and gate dimensions, profiles and roughness, and metal gate undercuts. Due to the finification process of FinFET devices, metrology models must now take into account the fins underlying the planar metrology pad, which provides additional challenges, and may lead to insufficient results.